ai infrastructure · max os

MAX OS — a derivation-first operating system.

An operating system written in MAX. Its memory and scheduling policies are derived from the same math the lab uses in its research — not hand-tuned heuristics, but mechanisms read out of theorems. Boots in QEMU as the compiler/OS engineering harness; the same driver-as-matrix design already runs on real silicon across four boards.

Why an OS

A research lab eventually wants to ask: if our math is right, what changes when the OS is built from it? MAX OS is that experiment. Page-replacement, scheduling, I/O ordering — all the places where a kernel makes a policy choice — are written as derivations from the lab's research, not as imported heuristics.

The honest goal is not to ship a desktop OS. It is to surface where derived policies beat tradition and where they do not. Both outcomes are valuable; both are reported.

What runs today

  • Boots cleanly in QEMU on ARM64.
  • EL1 kernel + EL0 userspace separation.
  • Process loader — reads /bin/hello from an ext2 disk and runs it in EL0.
  • Syscall surface for I/O and process exit.
  • ext2 read-write filesystem.

Honest results from the derived-policy experiments

A Kuramoto-style oscillator-coupled page-replacement policy outperformed the LRU baseline in its controlled benchmark. A separate cache-eviction policy derived from a different lab theorem under-performed LRU — twice. The lab reports both. Negative results are useful: they tell us which math actually carries the load and which does not.

Off QEMU and onto real silicon

The same driver-as-matrix design that boots in QEMU above is what runs on real boards under the MAX-OS silicon track — fully proven keyboard/mouse/network/Bluetooth on a Raspberry Pi 3B+; bare-metal GPU register access, a reached display coprocessor, and a bit-exact GEMM on a Jetson Orin; a camera-streaming wearable cortex on a Kendryte K230; boot and UART already answering on the real silicon of an Orange Pi R2S; and a bare-metal processing-system port plus hardware RTL accelerators on a Zynq-7020 FPGA. The QEMU build above is the engineering harness; the hardware page has the boards and the concrete per-board results.

Road to production-minimal

The remaining gates before this is a usable workstation OS are bounded: a text editor in userspace and persistent boot across power cycles. The plan is public on request.